Course description

Course Overview

This course provides an introduction to hardware modeling using Verilog, a hardware description language commonly used in the design and verification of digital systems. Participants will learn the basics of Verilog, and how to model and simulate hardware designs.

Key Learning Objectives

By the end of this course, participants will be able to:

• Understand the basics of hardware modeling
• Write and simulate Verilog code for digital system designs
• Understand the design hierarchy and code reusability
• Use Verilog for FPGA programming

Requirements

No prior knowledge of Verilog is required, but participants should be familiar with digital systems and have a basic understanding of programming concepts.

Outcomes

Upon completion of the course, participants will be able to:

• Write Verilog code to model digital systems
• Simulate and verify functionality of hardware designs
• Understand and implement design hierarchy and code reusability
• Transfer Verilog skills to FPGA programming

Certification

Participants will receive a certificate of completion upon finishing the course and fulfilling all requirements.

What will i learn?

• Understand the basics of hardware modeling
• Write and simulate Verilog code for digital system designs
• Understand the design hierarchy and code reusability
• Use Verilog for FPGA programming